The collaboration hopes to redefine digital storage, tackling the core of AI progress by reducing voltage in NAND flash technology through a new ferroelectric structure.

The rise of artificial intelligent (AI)-driven marvels hinges on cutting-edge data storage solutions. Without efficient data storage, applications like self-driving cars, life-saving healthcare diagnostics, and responsive voice assistants would fall short of their true potential.

At the forefront of this evolving data storage landscape, a collaboration between the Georgia Institute of Technology and Samsung seeks to substantially decrease the voltage in existing technology, unlocking the full potential of AI systems.

“Finding innovative solutions in data storage is paramount, it’s not just about saving photos or documents anymore. The storage needed is about enabling AI systems to transform how we interact with our devices, the world around us, and even each other,” said Asif Khan, an assistant professor in the School of Electrical and Computer Engineering (ECE) with a joint appointment in the School of Materials Science and Engineering (MSE).

Khan's lab is spearheading the collaboration which brings together three ECE labs, including those of Professors Suman Datta and Shimeng Yu. The lead author of the paper is Dipjyoti Das, a postdoctoral fellow under Khan's supervision. The second author, Hyeonwoo Park, conducts research under Datta. The team is joined by researchers from MSE, the Institute of Materials, the Institute of Electronics and Nanotechnology, and a dedicated team from Samsung.

“This is a pivotal era of transformation and opportunity in high-memory compute,” said co-author Suhwan Lim, an engineer at Samsung. “Strategic intersectoral relationships like this between Samsung and Georgia Tech nurture innovative thinking and lead to exciting experiential results that push us all forward.”

Adding to the already substantial Georgia Tech presence in the field of computer memory storage, the team's findings will be featured at the upcoming International Electron Devices Meeting (IEDM) in San Francisco this month.

The Quest for Voltage Efficiency

The research focuses on improving NAND flash technology found at the core of storage devices like solid-state hard drives, USB sticks, and SD cards. NAND boasts an impressive 1,000-layer 3D architecture, cramming 100 terabytes of data into a minuscule space.

However, the critical challenge is NAND’s persistent high voltage requirements. Exceeding 20 volts poses challenges in computing due to increased energy consumption, heat generation, and the risk of damaging electronic components.

“NAND has been the backbone of data storage, so our research doesn't attempt to replace it; it's an upgrade. We're boosting NAND's power and pushing it into the digital storage future,” said Das, who designed and executed experiments, as well as contributed to characterization.

A Ferroelectric Future

The paper’s groundbreaking proposal aims to revolutionize NAND flash technology by replacing the traditional NAND gate stack — a multi-layered structure in a transistor essential for controlling the flow of electrical current in semiconductor devices — with a new ferroelectric structure and a tunneling barrier.

The team's method, introducing aluminum oxide (Al2O3) in the middle of the ferroelectric stack, has dramatically improved data storage capability, reducing voltage requirements by an impressive 40-60%.

Additionally, the study reveals that the Al2O3 layer functions as a tunnel barrier, impeding electron motion and establishing a dipole, creating an additional electric field that aligns with the polarization direction, boosting device memory performance.

The experiential findings could transform various sectors, including AI, mobile devices, edge data processing, embedded systems, and overall computing efficiency. 

“This breakthrough charts a new course towards more efficient, reliable and dense data storage solution,” said Datta, who is the Joseph M. Pettit Chair of Advanced Computing in ECE and a Georgia Research Alliance (GRA) Eminent Scholar. “We are grateful to Samsung for their continued support, as we work towards the next milestone.”

Looking for Collective Solutions to Shared Challenges

According to Das, the approach not only demonstrates the capability to achieve reduced voltage and enhanced memory but also aligns with scalability and broad industry adoption. 

As the project ventures into commercial avenues, the input of Samsung's researchers will be crucial. Das and Park are actively uncovering the intricacies of disturbances that could impede the market acceptance of the new gate stack.

In this context, disturbances refer to any unintended disruptions or deviations from transistor behavior expectations. Das stresses the importance of understanding, controlling, and clearly defining disturbance specifications. Establishing a well-defined threshold for disturbances is pivotal for achieving widespread commercialization readiness in their research.

“Working alongside industry leaders like Samsung is essential for any endeavor aiming to make a transformative impact in everyday technology,” added Khan. “It becomes particularly pertinent as we collectively look towards a future dominated by the power required to fuel advancements in AI.”

Citation: Dipjyoti Das*, Hyeonwoo Park*, Zekai Wang, Chengyang Zhang, Prasanna Venkatesan Ravindran, Chinsung Park, Nashrah Afroze, Po-Kai Hsu, Mengkun Tian, Hang Chen, Winston Chern, Suhwan Lim, Kwangsoo Kim, Kijoon Kim, Wanki Kim, Daewon Ha; Shimeng Yu, Suman Datta, Asif Khan. “Experimental Demonstration and Modeling of a Ferroelectric Gate Stack with a Tunnel Dielectric Insert for NAND Applications.” Proceedings of the 2023 IEEE International Electron Devices Meeting (IEDM). Paper # 24.1