Sreejith Kochupurackal Rajan received the Best Student Paper Award at the 2019 IEEE International 3D Systems Integration Conference (3DIC), held October 8-10 in Sendai, Japan. Rajan is a Ph.D. student in the Georgia Tech School of Electrical and Computer Engineering (ECE) and is a member of the Integrated 3D Systems Group. 

The title of Rajan’s award winning paper is “High density and low-temperature interconnection enabled by mechanical self-alignment and electroless plating.” His coauthors on the paper are Ming Jui (Carl) Li, a fellow ECE Ph.D. student in the Integrated 3D Systems Group; Muhannad Bakir, Rajan’s and Li’s Ph.D. advisor and the Dan Fielder Professor in ECE; and Gary May, an ECE adjunct faculty member and chancellor of the University of California at Davis.

Modern compute workloads require hardware capabilities which cannot be provided by the ever-slowing transistor scaling. Especially, machine learning (ML) applications require densely integrated compute and memory fabric, which cannot be met with today's technologies. This has driven the recent surge towards heterogenous integration, where advanced 2.5D and 3D integrated circuits (ICs) complement System-on-Chip (SoC) innovations to provide high performance, low cost, and more customizable System-in-Packages (SiPs). In this work, Rajan and his coauthors present two key enabling technologies for SiP scaling.

Rajan and his coauthors present and discuss the use of mechanical self-alignment in conjunction with metal electroless deposition as a method to facilitate low temperature, low pressure, and high interconnect density inter-die bonding in heterogeneous 2.5D and 3D ICs. This method is a highly scalable alternative to the conventional solder-based interconnects, but comes without the stringent requirements including high temperature tolerance, high pressure process, extreme surface planarity and cleanliness, and very accurate initial alignment requirements of Cu-Cu (copper-copper) direct bonding. The conjunction with mechanical self-alignment, which has demonstrated sub-micron alignment accuracies, also helps scale the pitch easily, as well as provide a platform to create SiPs with a large number of individual chiplets.

Photo Information

Top photo: Sreejith Kochupurackal Rajan

Bottom photo: Sreejith Kochupurackal Rajan (right) is pictured with Professor Tetsu Tanaka of Tohoku University, Japan. Tanaka was a co-chair of the 2019 3DIC Conference