NAND flash memory is the foundation of modern digital storage, powering everything from smartphones to large-scale cloud infrastructure. As artificial intelligence, edge computing, and data-centric applications continue to grow, the demand for high-density, low-latency, and energy-efficient memory solutions is more critical than ever.

While vertical 3D NAND architecture has scaled storage to hundreds of layers, further advancement is limited by challenges in retention, endurance and operating voltage. Emerging technologies like ferroelectric NAND (FE-NAND) and advanced gate stack engineering also offer promising solutions, but retention reliability remains a key hurdle.

At the 2025 IEEE International Reliability Physics Symposium (IRPS), research led by Georgia Tech School of Electrical and Computer Engineering (ECE) Ph.D. student Prasanna Venkatesan, received the Best Paper Award for tackling these challenges.

The paper titled, “Enhanced Memory Performance in Ferroelectric NAND Applications: The Role of Tunnel Dielectric Position for Robust 10-year Retention,” presents a comprehensive experimental and simulation-based study on retention loss in FE-NAND devices. 

The research, conducted in ECE professor Asif Khan’s research group, in collaboration with the University of Modena and Reggio Emilia, and industry partners Samsung Electronics, Micron, and Applied Materials, reveals that the position of the inserted dielectric layer within the ferroelectric stack is critical.

By placing a tunnel dielectric layer (TDL) in the middle of the stack—rather than adjacent to the gate—the team achieved significant improvements in charge stability and suppression of depolarization-driven memory window loss. The study reports less than one percent degradation over a 10-year projected period, supporting quad-level cell (QLC)-compatible operation with robust long-term retention.

This award-winning work highlights the growing importance of ferroelectric memory technologies in shaping the future of high-density, scalable, and energy-efficient non-volatile storage.

Prasanna Venkatesan received his B.Tech degree in electrical engineering from the Indian Institute of Technology (IIT) Palakkad in 2019. His research interests lie at the intersection of electrical engineering and materials science, with a strong focus on ferroelectrics. He is currently working on advancing ferroelectric technologies for applications in NAND (band-engineered FEFETs), DRAM (ferroelectric capacitors), and embedded memory (FEFETs).