ECE Ph.D. student Debashis Banerjee will receive a Best in Track Paper Award at the 2014 IEEE/ACM International Conference on Computer-Aided Design, to be held November 2-6 in San Jose, California. 

Debashis Banerjee will receive a Best in Track Paper Award at the 2014 IEEE/ACM International Conference on Computer-Aided Design, to be held November 2-6 in San Jose, California. Banerjee is a Ph.D. student in the Georgia Tech School of Electrical and Computer Engineering (ECE).

The title of Banerjee’s award-winning paper is “Self-Learning MIMO-RF Receiver Systems: Process Resilient Real-Time Adaptation to Channel Conditions for Low Power Operation,” coauthored by his fellow ECE Ph.D. students – Shreyas Sen, Barry Muldrey, Xian Wang – and ECE Professor Abhijit Chatterjee, who serves as the Ph.D. advisor for all of the student authors, including Banerjee.

Prior research has established that dynamically trading-off the performance of the RF front-end for reduced power consumption across changing channel conditions, using a feedback control system that modulates circuit and algorithmic level “tuning knobs” in real-time, leads to significant power savings. Optimal power control strategy also depends on the process conditions corresponding to the involved RF devices. This factor complicates the problem of designing the feedback control system that guarantees the best control strategy for minimizing power consumption across all channel conditions and process corners.

Since this problem is largely intractable due to the complexity of simulation across all channel conditions and process corners, Banerjee and his coauthors have proposed a “self-learning” strategy for adaptive MIMO-RF systems in this paper. In this approach, RF devices learn their own performance vs. power consumption vs. tuning knob relationships “on-the-fly” and formulate the optimum reconfiguration strategy using neural-network-based learning techniques during real-time operation. The methodology is demonstrated for a MIMO-RF receiver front-end and is supported by hardware validation leading to significant power savings in minimal learning time.