Research from the Georgia Tech School of Electrical and Computer Engineering hopes to pioneer a new generation of 3D ferroelectric memory (FeRAM).

Ph.D. student Eknath Sarkar recently won the Best Demonstration Award at the 2025 Center for Processing with Intelligent Storage and Memory (PRISM) Annual Review for his study, “Monolithic Two-Tier Dual Gated Ga-doped In2O3 1T-1C Memory Cell for Bit Cost Scalable 3D FeRAM.”

Modern computing—especially for artificial intelligence (AI)—relies heavily on memory that can store and retrieve vast amounts of data quickly. Today’s most common memory, dynamic random access memory (DRAM), requires constant refreshing to preserve information, consuming significant power.

Ferroelectric RAM (FeRAM) is different. It can store data without continuous updates, saving energy. But traditional flat designs cannot keep pace with the rapidly growing memory demands of AI and edge computing.

“Just as cities grow upward by constructing taller buildings, FeRAM must be built in three dimensions, stacking memory cells vertically to pack more capacity into the same footprint,” Eknath said. “Achieving this, however, is extremely challenging because each stacked layer must function consistently, and the materials used must survive sensitive, low-temperature processing.”

Completed in Professor Suman Datta’s Semiconductor Technology Advanced Research Laboratory, the project achieved promising results by vertically stacking two complete FeRAM cells, achieving excellent layer-to-layer uniformity, low-voltage write and read operation, and a scalable path toward monolithic 3D memory.

It marks the first time a two-tier FeRAM cell has been built using ultra-thin ferroelectric films (5-nm HfZrO₂) integrated with advanced dual-gate Ga-doped In₂O₃ transistors —all fabricated in the Georgia Tech academic cleanroom.

This research further shows fast, energy-efficient reading methods that don’t damage stored data. Together, these advances represent a major step toward high-density, 3D-integrated memory systems that combine the speed of DRAM with the energy savings of FeRAM, according to Eknath.

PRISM is led by the University of California, Santa Barbara, and focuses on memory and storage. It is part of the Semiconductor Research Corporation’s Joint University Microelectronics Program 2.0, in cooperation with the Defense Advanced Research Projects Agency.