Research on a new 3D field-programmable gate array (FPGA) design tool from Georgia Tech School of Electrical and Computer Engineering (ECE) Ph.D. students won the William J. McCalla Front-End Best Paper Award at the 2025 International Conference on Computer-Aided Design held in Munich, Germany, from Oct. 26 – Oct. 30.

The tool, named LaZagna, provides researchers with an open, flexible platform for 3D FPGA exploration. It was developed by Ismael Youssef and Hang Yang in Assistant Professor Callie Hao’s Software/Hardware Co-Design for Intelligence and Efficiency (Sharc) Lab.

FPGAs are configurable integrated circuits that can be repeatedly programmed after manufacturing and have a wide range of uses across a number of industries. These include artificial intelligence acceleration, wireless communications, medical imaging, chip prototyping, aerospace, and defense.

At the same time, 3D integrated circuits (3D ICs) have become a rapidly growing area of research, as technology starts to eclipse the expected innovation outlined in Moore’s Law, which observed the number of transistors in ICs doubling about every two years.

3D FPGAs are the result of combining these two technologies. It is achieved by stacking multiple FPGAs on top of each other.

They have been found to outperform their 2D counterparts but still suffer from design bottlenecks that slow advancements, according to Youssef. That is where he and Yang wanted to help fill in the gaps.

“The fundamental question we wanted to answer was, what does a 3D FPGA look like?” Youssef said. “While there had been some work in the past, there was no comprehensive study or framework for such exploration.”

LaZagna provides an end-to-end design flow that generates both the digital models for 3D FPGA architectures and the bitstream to program them. It also exposed a massive design space, with over a billion different 3D FPGA architecture possibilities.

“This allows researchers to move beyond simulation into actual physical design, evaluate real-world viability, and push the boundaries of FPGA architecture into the third dimension,” Youssef said. “Our goal wasn’t to declare the ‘best’ 3D FPGA design, but rather to enable the research community to explore and identify promising directions.”

LaZagna is available for any researchers to use, with the goal of them being able to build on it.

As the Sharc Lab continuines to work on LaZagna and other 3D FPGA-related research, they hope to expand the tool’s architecture space to model novel 3D architectures that haven’t yet been explored.