Georgia Tech School of Electrical and Computer Engineering (ECE) Ph.D. students Jiho Kim and Danish Baig were awarded a 2025 Qualcomm Innovation Fellowship (QIF).

Their proposal, “Network-on-X (NoX): Hierarchical Interconnect Modeling & DSE for 2.5D/3D Chiplet Architectures,” was one of only 17 selected from a highly competitive pool of 266 submissions across North America, and the only winning team from Georgia Tech.

Kim and Baig’s project, NoX, addresses a critical gap in modern chiplet-based system design. As the industry shifts toward 2.5D and 3D integration, existing tools fail to account for the intricate interactions between architecture and packaging. NoX proposes a cross-layer simulation framework that models hierarchical communication while incorporating real-world packaging constraints—enabling more accurate and scalable design space exploration for AI and high-performance computing (HPC) systems.

The QIF program invests in Ph.D. students across a broad range of technical research areas, empowering them to take steps toward achieving their research goals. The fellowship will provide Baig and Kim with one year of support to pursue their research, as well as offer mentorship from Qualcomm engineers.

Kim is advised by Professor Cong (Callie) Hao in the Sharc Lab. Her research focuses on field programmable gate arrays design and architecture-packaging co-design, with an emphasis on developing technology-aware simulators for emerging chiplet-based systems. She interned at IBM Research in 2024 and will be a visiting scholar at ETH Zurich this summer. Her recent work was nominated for Best Paper at 2025 IEEE International Symposium on Field-Programmable Custom Computing Machines.

Baig is advised by ECE professor Muhannad Bakir at the Integrated 3D Systems Lab. He received his B.A. in nanotechnology engineering from the University of Waterloo in Canada, after which he worked as an optoelectronics design engineer and patented novel techniques for large-area printing of microdevices. His current research focuses on chiplet bonding using nanoscale interconnects. He is on a summer internship at Analog Devices as an advanced packaging intern.