Shimeng Yu is an associate professor of electrical and computer engineering at the Georgia Institute of Technology. He received the B.S. degree in microelectronics from Peking University in 2009, and the M.S. degree and Ph.D. degree in electrical engineering from Stanford University in 2011 and 2013, respectively. From 2013 to 2018, he was an assistant professor at Arizona State University.
Prof. Yu’s research interests are nanoelectronic devices and circuits for energy-efficient computing systems. His expertise is on the emerging non-volatile memories (e.g., RRAM, ferroelectrics) for different applications such as deep learning accelerator, neuromorphic computing, monolithic 3D integration, and hardware security.
Among Prof. Yu’s honors include the NSF Faculty Early CAREER Award in 2016, the IEEE Electron Devices Society (EDS) Early Career Award in 2017, the ACM Special Interests Group on Design Automation (SIGDA) Outstanding New Faculty Award in 2018, the Semiconductor Research Corporation (SRC) Young Faculty Award in 2019, and the ACM/IEEE Design Automation Conference (DAC) Under-40 Innovators Award in 2020.
Prof. Yu is active in professional services. He served or is serving with many premier conferences on technical program committees, including the IEEE International Electron Devices Meeting (IEDM), IEEE Symposium on VLSI Technology, ACM/IEEE Design Automation Conference (DAC), ACM/IEEE Design, Automation & Test in Europe (DATE), and ACM/IEEE International Conference on Computer-Aided-Design (ICCAD). He is a senior member of the IEEE.
- Nanoelectronic Devices
- Non-volatile Memories
- Integrated Circuit Design
- Electronic Design Automation (EDA)
- Deep Learning Accelerator
- Hardware Security
- ACM/IEEE Design Automation Conference (DAC) Under-40 Innovators Award, 2020
- Semiconductor Research Corporation (SRC) Young Faculty Award, 2019
- ACM Special Interest Group on Design Automation (SIGDA) Outstanding New Faculty Award, 2018
- IEEE Electron Devices Society (EDS) Early Career Award, 2017
- ASU Fulton Outstanding Assistant Professor, 2017
- NSF Faculty Early Career Development (CAREER) Award, 2016
- DoD-Defense Threat Reduction Agency (DTRA) Young Investigator Award, 2015
H. Jiang, S. Huang, X. Peng, J.-W. Su, Y.-C. Chou, W.-H. Huang, T.-W. Liu, R. Liu, M.-F. Chang, S. Yu, “A two-way SRAM array based accelerator for deep neural network on-chip training,” ACM/IEEE Design Automation Conference (DAC), 2020.
S. Yu, X. Sun, X. Peng, S. Huang, “Compute-in-memory with emerging nonvolatile-memories: challenges and prospects,” IEEE Custom Integrated Circuits Conference (CICC), 2020.
P. Wang, Z. Wang, W. Shim, J. Hur, S. Datta, A. I. Khan, S. Yu, “Drain-erase scheme in ferroelectric field effect transistor - Part I: device characterization,” IEEE Trans. Electron Devices, vol. 67, no. 3, pp. 955-961, 2020.
P. Wang, W. Shim, Z. Wang, J. Hur, S. Datta, A. I. Khan, S. Yu, “Drain-erase scheme in ferroelectric field effect transistor-Part II: 3D-NAND architecture for in-memory computing,” IEEE Trans. Electron Devices, vol. 67, no. 3, pp. 962-967, 2020.
X. Peng, S. Huang, Y. Luo, X. Sun, S. Yu, “DNN+NeuroSim: An end-to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies,” IEEE International Electron Devices Meeting (IEDM), 2019.
J. Woo, P. Wang, S. Yu, “Integrated crossbar array with resistive synapses and oscillation neurons,” IEEE Electron Device Lett., vol. 40, no. 8, pp.1313-1316, 2019.
R. Liu, X. Peng, X. Sun, W.-S. Khwa, X. Si, J.-J. Chen, J.-F. Li, M.-F. Chang, S. Yu, “Parallelizing SRAM arrays with customized bit-cell for binary neural networks,” ACM/IEEE Design Automation Conference (DAC), 2018.
S. Yu, “Neuro-inspired computing with emerging non-volatile memory,” Proc. IEEE, vol. 106, no. 2, pp. 260-285, 2018.
X. Sun, P. Wang, K. Ni, S. Datta, S. Yu, “Exploiting hybrid precision for training and inference: a 2T-1FeFET based analog synaptic weight cell,” IEEE International Electron Devices Meeting (IEDM), 2018.
P.-Y. Chen, X. Peng, S. Yu, “NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures,” IEEE International Electron Devices Meeting (IEDM), 2017.
S. Yu, P.-Y. Chen, “Emerging memory technologies: recent trends and prospects,” IEEE Solid State Circuits Magazine, vol. 8, no. 2, pp. 43-56, 2016.
Last revised October 28, 2021