David Keezer is a professor emeritus in the School of Electrical and Computer Engineering at Georgia Tech and a Life Fellow of the IEEE. He is currently a chair professor in the College of Information Science and Technology and a founding faculty of Eastern Institute of Technology, Ningbo, China. He received the B.A. degree from the University of California, Berkeley, CA, USA, the M.S. degree from the California Institute of Technology, Pasadena, CA, USA, the Ph.D. degree from Carnegie-Mellon University, Pittsburgh, PA, USA, and the M.B.A. degree from the Florida Institute of Technology, Melbourne, FL, USA. Prior to joining Georgia Tech, he was an Associate Professor with the University of South Florida, Tampa, FL, USA and was with Harris Corporation, Englewood, CO, USA, Intel Corporation, Santa Clara, CA, USA, and IBM Corporation, Armonk, NY, USA. He joined the Georgia Institute of Technology, Atlanta, GA, USA, in 1995, where he was a professor of electrical and computer engineering. He has authored over 250 articles on electronics testing. His current research interests include the design and test of high-performance electronic systems.
- 1979-1983, Carnegie-Mellon University, Electrical Engineering (PhD)
- 1978-1979, California Institute of Technology, Applied Physics (MS)
- 1975-1978, University of California at Berkeley, Physics and Applied Mathematics (BA)
- 1983-1985, Florida Institute of Technology, Master of Business Administration (MBA)
David Keezer's research primarily focuses on advancing electronics testing methodologies, especially for high-speed (GHz-THz) digital integrated circuits. He has contributed to the development of high-performance automated test equipment (ATE) to enhance testing speed and accuracy at reduced costs. Additionally, he has worked on the development of advanced VLSI testing techniques, fault detection, test methods for advanced packaging electronic systems, and system reliability.
Professor Keezer’s work has had a lasting impact on the field of electronics testing, particularly for high-speed digital ICs and systems. He is known for developing new test methodologies that address the challenges posed by increasingly fast and complex digital circuits.
At Georgia Tech, he created the Advanced Digital Systems Test course, which focuses on high-speed digital circuits and automated testing techniques. He also developed a special topics course on Advanced Technology Forecasting, exploring the future of key technologies like genetics, nanotechnology, and robotics (AI). Professor Keezer has taught at Georgia Tech's Shenzhen campus in China and developed courses at the University of South Florida, including High-Speed Digital Design and Test and Design and Test of Digital GaAs Circuits. His courses are known for their hands-on approach and exceptional student experience.
- West Lake International Friendship Award from Zhejiang Province Government (2025)
- IEEE Life Fellow (2024)
- IEEE Fellow (2010) - Awarded for contributions to high-speed digital test technology.
- IEEE International Test Conference (ITC) Contribution Awards (1990-2025) - Recognized numerous times for technical contributions to the ITC program.
- IEEE Computer Society Certificate of Appreciation (2007) - For serving as General Chair for the Gigahertz Test Workshop (GTW) 2007.
- IEEE 14th Asian Test Symposium Contribution Award (2005) - For the paper “A 5 Gbps Wafer-Level Tester.”
- IEEE Computer Society Certificate of Appreciation (2005) - For serving as Technical Program Chair for the GHz/Gbps Test Workshop.
- IEEE Transactions on Advanced Packaging Commendable Paper Award (2005) - For the paper “The SOP for Miniaturized, Mixed-Signal Computing, Communication, and Consumer Systems of the Next Decade.”
- IEEE Computer Society Golden Core Member Award (2005) - Recognized as a Golden Core Member.
- IEEE Computer Society Continuous Services Award (2004) - For ten years of outstanding service to the IEEE ITC Program Committee.
- Top-Ten Paper for IEEE International Test Conference (2004) - For the paper “A Production-Oriented Multiplexing System for Testing at 2.5 Gbps.”
- IEEE International Mixed Signal Workshop Certificate of Appreciation (2004) - For serving on the program committee.
- IEEE Senior Member (2003) - Elevated to Senior Member status before becoming a Fellow in 2010.
- EDAPS Invited Speaker Award (2002) - Awarded for contributions as an invited speaker.
- IEEE/EIA Certificate of Appreciation (2001) - For outstanding contributions to the 51st Electronics Components and Technology Conference.
- Tenure at Georgia Institute of Technology (1999) - Granted tenure at Georgia Tech.
- Tenure at Univ of South Florida (1995).
- University of South Florida Honored Researcher (1990-1995) - Honored as an active researcher at USF six consecutive years.
- Harris Corporation "PEOPLE Program" Award (1988) - For leading the "Test Cost Reduction" project, for significantly reducing the cost of developing tests for VLSI.
- Harris Corporation Engineering Award (1987) - For enhancing E-Beam Voltage Contrast for ASIC failure analysis.
- IBM Pre-doctoral Fellowship (1980-1982) - Awarded the pre-doctoral fellowship at Caltech and Carnegie Mellon University for study of domain dynamics of magnetic memory devices.
- Northrop Corporate Fellowship (1978-1979) - Awarded the fellowship at California Institute of Technology.
- A Data-Driven Approach to Online Fault Detection in RRAM-based Neuromorphic Hardware using Adversarial-Inspired Test, M. Cheng, X.-C. Li, and D. Keezer, IEEE Transactions on Very Large Scale Integration Systems, 2026.
- Bidirectional Time-Frequency Modulation Sampling Technique for High-Efficiency Phase Measurement, C. Wang, S. Liu, Y. Xiao, X. Li, and D. Keezer, IEEE Transactions on Instrumentation and Measurement, 2026.
- A Low-Loss and Ultra-Wideband Dual-Signal Air-Filled Transmission Line for Terahertz Applications, C. Wang, X.-C. Li, and David Keezer, IEEE Trans. Microw. Theory Techn., 2025.
- Low-Cost 20 Gbps Digital Test Signal Synthesis Using SiGe and InP Logic, D.C. Keezer, C.E. Gray, D. Minier, P. Ducharme, Journal of Electronics Test Theory and Applications (JETTA), January 2010.
- A 5 Gbps Test System for Wafer-Level Packaged Devices, A. M. Majid, D. C. Keezer, IEEE Trans. on Electrical Packaging Manufacturing (TEPM), Vol.32, No.3, pp. 144-151, July 2009.
- Source-Synchronous Testing of Multilane PCI Express and Hyper-Transport Buses, D.C. Keezer, D. Minier, P. Ducharme, IEEE Design and Test of Computers, vol. 23, no. 1, pp. 46-57, January 2006.
- Low-Cost Strategies for Testing Multi-GigaHertz SOPs and Components, D.C. Keezer, J.S. Davis, S. Bezos, D. Minier, M.C. Caron, K. Bergman, IEEE Transactions on Advanced Packaging, 2005.
- Multiplexing ATE Channels for Production Testing at 2.5 Gbps, D.C. Keezer, D. Minier, M.C. Caron, IEEE Design and Test of Computers, Vol.21 No.4, pp. 288-301, July/August 2004.
- The SOP for Miniaturized, Mixed-Signal Computing, Communication, and Consumer Systems of the Next Decade, R.R. Tummala, M. Swaminathan, M. Tentzeris, J. Laskar, G.K. Chang, S. Sitaraman, D. Keezer, D. Guidotti, Z. Huang, K. Lim, L. Wan, S. Bhattacharya, V. Sundaram, F. Liu, P.M. Raj, IEEE Trans. On Adv. Packaging, Vol. 27, No. 2, pp. 250-267, May 2004.
- Electrical Test Strategies for a Wafer-Level Packaging Technology, D.C. Keezer, C.S. Patel, M.S. Bakir, Q. Zhou, J.D. Meindl, IEEE Trans. on Electronics Packaging Manufacturing, Vol. 26, No. 4, pp. 267-272, October 2003.