VLSI and Advanced Digital Design

(3-0-3-4)

CMPE Degree: This course is Selected Elective for the CMPE degree.

EE Degree: This course is Selected Elective for the EE degree.

Lab Hours: 3 supervised lab hours and 0 unsupervised lab hours.

Technical Interest Groups / Course Categories: Threads / ECE Electives

Course Coordinator: Nivedita Bhattacharya

Prerequisites: ECE 2031 [min C] and ECE 2040 [min C]

Catalog Description

Advanced digital design issues in the context of VLSI systems. Introduction to a design methodology that encompasses the range from architectural models to circuit simulation.

Textbook(s)

Modern VLSI Design: IP-Based Design, Logical Effort: Designing Fast CMOS Circuits

Course Outcomes

Demonstrate a clear understanding of important concepts in CMOS technology and fabrication that affect design. 

Design a gate of any given arbitrary logic function at the transistor-level. 

Layout a gate in CMOS VLSI technology. 

Size the gates of the given VLSI layout to minimize the delay. 

Design a network of complex gates with the ideal number of stages that computes the function with minimum delay. 

Simulate a VLSI design in SPICE to obtain delay and power performance measures.

Find a test vector to test given faults in a logic network.

Design and characterize synchronized circuits for asynchronous external inputs. 

Design and layout a variety of adders and multipliers. 

Analyze and simulate interconnect delay. 

Design and layout a datapath that consists of various functional, memory, communication, and interface units.

Understand system issues such as floorplanning and power/ground distribution

Strategic Performance Indicators (SPIs)

N/A

Topic List

  1. Design Methodology (1 week)
  2. Switches and Layout (3 weeks)
    1. Switch based design
    2. Complex gates
    3. Layout and technology
    4. Registers
    5. Adders
  3. Ciruit design issues (4 weeks)
    1. MOSFET models
    2. Delay models
    3. Hazards, metastability, synchronization
    4. Alternate logic structures
    5. Timing and clocking
    6. Power models
    7. Sleep transistors
  4. Advanced digital issues (3 weeks)
    1. Logical effort
    2. Ideal number of stages
    3. Asymmetric gates
    4. Calibrating the model
    5. Branches and Interconnect
  5. Test Logic (1 week)
    1. Combinational test
    2. Sequential test
    3. Scan design
  6. Advanced Modules (2 weeks)
    1. ROM, PLA
    2. Advanced adders
    3. Multipliers
    4. Barrel shifter
    5. Decoders