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Photo file: 
Full name: 
Tom Conte
Job title: 
Associate Dean-Academic
Technical Interest Groups: Computer Systems and Software, VLSI Systems and Digital Design
Email address: 
Work phone: 
Klaus 2334

Tom Conte holds a joint appointment in the Schools of Electrical & Computer Engineering and Computer Science at the Georgia Institute of Technology. He is the founding director of the Center for Research into Novel Computing Hierarchies (CRNCH). His research is in the areas of computer architecture and compiler optimization, with emphasis on manycore architectures, microprocessor architectures, back-end compiler code generation, architectural performance evaluation and embedded computer system architectures.

Prior to joining Georgia Tech in 2008, Dr. Conte served as director of the Center for Embedded Systems Research and was on the faculty in the Department of Electrical and Computer Engineering at North Carolina State University, beginning in 1995.

Dr. Conte was the 2015 President of the Institute of Electrical and Electronics Engineering (IEEE) Computer Society, and also a fellow of the IEEE. Since 2011, he has co-led the IEEE Rebooting Computing Initiative.

Dr. Conte received his bachelor's degree in electrical engineering from the University of Delaware in 1986, and he received his M.S. and Ph.D. degrees in electrical engineering from the University of Illinois at Ubana-Champaign in 1988 and 1992, respectively.

Research interests: 
  • Computer architecture
  • Compiler optimization
  • IEEE Computer Society's Golden Core Member award
  • IEEE Fellow (citation: “for contributions to computer architecture, compiler code generation and performance evaluation”)
  • Young Alumni Achievement Award, Dept. of ECE, University of Illinois at Urbana-Champaign, 2004
  • National Science Foundation Faculty Early Career Development (CAREER) Award, 1996

US Patent No. 7,953,955, "Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture," S. Y. Larin, P. G. Pechanek and T. M. Conte, issued May 31, 2011, 14 claims.

J. A. Poovey, B. P. Railing and T. M. Conte, "Parallel pattern detection for architectural improvements," Proceedings of the 3rd USENIX Workshop on Hot Topics in Parallelism (HotPar), (Berkeley, CA), May 26–27, 2011.

B. V. Iyer and T. M. Conte, "On power and energy trends of IEEE 802.11n PHY," Proceedings of the 12th International ACM Symposium on Modeling Analysis and Simulation of Wireless and Mobile Systems (MSWiM 2009), (Tenerife, Canary Islands, Spain), Oct. 26-19, 2009.

J. A. Poovey, M. Levy, S. Gal-On, T. M. Conte, "A benchmark characterization of the EEMBC benchmark suite," IEEE Micro, Sep.-Oct. '09.

B. V. Iyer, J. G. Beu, and T. M. Conte, "Length Adaptive Processors: The solution for Energy/Performance Dilemma in Embedded Systems," INTERACT-13: Workshop on Interaction Between Compilers and Computer Architecture (Held in Conjunction with HPCA), (Raleigh, NC), Feb 16th, 2009.

B. V. Iyer, J. A. Poovey and T. M. Conte, "Energy-Aware Opcode Design," in Proceedings of the 26th International Conference on Computer Design, (Lake Tahoe, California), Oct. 12-15, 2008.

B. V. Iyer and T. M. Conte, "A Power Model for Register-Sharing Structures," in Proceedings of the 2008 IFIP Working Conference on Distributed and Parallel Embedded Systems, (Milano, Italy), Sep. 2008.

P. D. Bryan and T. M Conte, "Combining Cluster Sampling with Single Pass Methods for Efficient Sampling Regimen Design," in Proceedings of the 2007 International Conference, on Computer Design, (Lake Tahoe, CA), Oct. 2007.

P. D. Bryan, M. C. Rosier and T. M Conte, "Reverse State Reconstruction for Sampled Microarchitectural Simulation," in Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software (San Jose, CA), April 2007.

M. C. Rosier and T. M. Conte, "Treegion Instruction Scheduling in GCC," in Proceedings of the 2006 GCC Developers' Summit, (Ottawa, Canada), June 2006.

S. Sharma, J. G. Beu and T. M. Conte, "Spectral prefetcher: An effective mechanism for L2 cache prefetching," ACM Transactions on Architecture and Code Optimization, vol. 2 , no. 4, Dec. '05, pp. 423-450.

E. Ozer and T. M. Conte, "High-performance and low-cost dual-thread VLIW processor using WELD architecture paradigm," IEEE Transactions on Parallel and Distributed Systems, vol. 16, no. 12, Dec. '05.

H. Zhou and T. M. Conte, "Enhancing memory-level parallelism via recovery-free value prediction," IEEE Transactions on Computers, vol. C-54, no. 7, Jul. '05, pp. 897-912.

Last revised January 31, 2023