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Photo file: 
photograph of Callie Hao
Full name: 
Callie Hao
Job title: 
Assistant Professor
; Sutterfield Family Early Career Professor
Technical Interest Groups: Computer Systems and Software, VLSI Systems and Digital Design
Email address: 
Klaus 2306

Dr. Cong (Callie) Hao is an assistant professor in ECE at Georgia Tech, where she currently holds the Sutterfield Family Early Career Professorship. She was a postdoctoral fellow in the School from 2020-2021 and also worked as a postdoctoral researcher in ECE at the University of Illinois at Urbana-Champaign from 2018-2020. She received the Ph.D. degree in Electrical Engineering from Waseda University in 2017, and the M.S. and B.S. degrees in Computer Science and Engineering from Shanghai Jiao Tong University.

Dr. Hao believes in the power of software/hardware co-design. Her primary research interests lie in the joint area of efficient hardware design and machine learning algorithms. She is passionate about reconfigurable and high-efficiency computing and building useful electronic design automation tools.

Dr. Hao is a big fan of outdoor activities, especially mountain climbing, long distance hiking, cycling, and running. She is also a passionate but amateur Judo player.

Research interests: 
  • Reconfigurable computing and FPGA accelerators
  • Hardware-aware machine learning (GNNs, DNNs)
  • Electronic design automation (HLS)
  • Third place winner in IEEE DAC-SDC, 2020
  • Double-championship in IEEE DAC-SDC, 2019
  • Third place winner in IEEE DAC-SDC, 2018
  • Best Student Paper in IEEE International New Circuits and Systems Conference, 2016
  • Best student paper in IEEE International Conference on ASIC, 2015 and 2013

Lixiang Li, Yao Chen, Zacharie Zirnheld, Pan Li, and Cong Hao. “MeLoPPR: Software/Hardware Co-design for Memory-efficient Low-latency Personalized PageRank”, IEEE/ACM DAC, 2021

Cong Hao, Chen Yao, Xiaofan Zhang, Yuhong Li, Jinjun Xiong, Wen-mei Hwu, and Deming Chen. "Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devices." IEEE GLSVLSI, 2020

Yuhong Li*, Cong Hao*, Xiaofan Zhang, Chen Yao, Jinjun Xiong, Wen-mei Hwu and Deming Chen, "EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions", IEEE/ACM DAC, 2020

Cong Hao, Yao Chen, Xinheng Liu, Atif Sarwari, Daryl Sew, Ashutosh Dhar, Bryan Wu, Dongdong Fu, Jinjun Xiong,Wen-mei Hwu, Junli Gu and Deming Chen, "NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving", IEEE/ACM ICCAD, 2019

Cong Hao, Xiaofan Zhang, Yuhong Li, Sitao Huang, Jinjun Xiong, Kyle Rupnow, Wen-Mei Hwu, and Deming Chen,"FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge", IEEE/ACM DAC, 2019

Last revised January 12, 2022