Silicon-Based Heterostructure Devices and Circuits


CMPE Degree: This course is Not Applicable for the CMPE degree.

EE Degree: This course is Not Applicable for the EE degree.

Lab Hours: 0 supervised lab hours and 0 unsupervised lab hours.

Technical Interest Group(s) / Course Type(s): Electronic Design and Applications, Nanotechnology

Course Coordinator: John D Cressler

Prerequisites: ECE 3040 (required) and ECE 3450 (optional)

Corequisites: None.

Catalog Description

Theory and design of novel silicon-germanium microelectronic devices and circuits. Materials, device physics, fabrication, measurement, circuit design, and system applications.

Course Outcomes

Not Applicable

Student Outcomes

In the parentheses for each Student Outcome:
"P" for primary indicates the outcome is a major focus of the entire course.
“M” for moderate indicates the outcome is the focus of at least one component of the course, but not majority of course material.
“LN” for “little to none” indicates that the course does not contribute significantly to this outcome.

1. ( Not Applicable ) An ability to identify, formulate, and solve complex engineering problems by applying principles of engineering, science, and mathematics

2. ( Not Applicable ) An ability to apply engineering design to produce solutions that meet specified needs with consideration of public health, safety, and welfare, as well as global, cultural, social, environmental, and economic factors

3. ( Not Applicable ) An ability to communicate effectively with a range of audiences

4. ( Not Applicable ) An ability to recognize ethical and professional responsibilities in engineering situations and make informed judgments, which must consider the impact of engineering solutions in global, economic, environmental, and societal contexts

5. ( Not Applicable ) An ability to function effectively on a team whose members together provide leadership, create a collaborative and inclusive environment, establish goals, plan tasks, and meet objectives

6. ( Not Applicable ) An ability to develop and conduct appropriate experimentation, analyze and interpret data, and use engineering judgment to draw conclusions

7. ( Not Applicable ) An ability to acquire and apply new knowledge as needed, using appropriate learning strategies.

Strategic Performance Indicators (SPIs)

Outcome 1 (Students will demonstrate expertise in a subfield of study chosen from the fields of electrical engineering or computer engineering):
1. Understand the history and evolution of Si/SiGe heterostructure technology
2. Understand physics of Si/SiGe devices

Outcome 2 (Students will demonstrate the ability to identify and formulate advanced problems and apply knowledge of mathematics and science to solve those problems):
1. Assess the dependence of Si/SiGe devices on SiGe material layer composition
2. Quantify changes in circuit-relevant performance metrics (gain, noise, linearity)

Outcome 3 (Students will demonstrate the ability to utilize current knowledge, technology, or techniques within their chosen subfield):
1. Determine best circuit types suited for use in Si/SiGe technology
2. Quantify circuit performance leverage and tradeoffs for these circuits

Course Objectives

Topical Outline

1. Introduction
a. historical perspective
b. application-induced device design constraints
c. bandgap engineering in the Si material system
d. SiGe vs III-V vs Si
e. the state-of-the-art
2. Epitaxial SiGe Alloys
a. strained-layer epitaxy
b. stability constraints
c. growth techniques
d. band structure and band alignments
e. carrier transport properties
3. The SiGe Heterojunction Bipolar Transistor (SiGe HBT)
a. review of Si BJT device physics
b. device fabrication and structural design
c. process integration issues with CMOS
d. dc and ac properties
e. second-order device phenomena
f. temperature effects
4. Circuit Design with SiGe HBTs
a. application-driven profile optimization
b. low-frequency noise
c. broadband noise
d. linearity
e. compact modeling issues
f. design example: a SiGe HBT LNA
5. Other Si-Based Heterostructure Devices
a. SiGe-channel FETs
b. strained-Si CMOS
c. SiGe-based resonant tunneling devices
d. SiGe-based optoelectronics devices
6. Future Directions