Computer-Aided VLSI System Design


CMPE Degree: This course is Not Applicable for the CMPE degree.

EE Degree: This course is Not Applicable for the EE degree.

Lab Hours: 0 supervised lab hours and 0 unsupervised lab hours.

Technical Interest Group(s) / Course Type(s): VLSI Systems and Digital Design

Course Coordinator: Vincent J Mooney

Prerequisites: ECE 3150

Corequisites: None.

Catalog Description

Theory and practice of computer-aided VLSI digital systems design. Logic
synthesis, semi-custom VLSI design, high-level synthesis, low power systems
and hardware/software co-design. Individual/group projects.

Course Outcomes

Not Applicable

Student Outcomes

In the parentheses for each Student Outcome:
"P" for primary indicates the outcome is a major focus of the entire course.
“M” for moderate indicates the outcome is the focus of at least one component of the course, but not majority of course material.
“LN” for “little to none” indicates that the course does not contribute significantly to this outcome.

1. ( Not Applicable ) An ability to identify, formulate, and solve complex engineering problems by applying principles of engineering, science, and mathematics

2. ( Not Applicable ) An ability to apply engineering design to produce solutions that meet specified needs with consideration of public health, safety, and welfare, as well as global, cultural, social, environmental, and economic factors

3. ( Not Applicable ) An ability to communicate effectively with a range of audiences

4. ( Not Applicable ) An ability to recognize ethical and professional responsibilities in engineering situations and make informed judgments, which must consider the impact of engineering solutions in global, economic, environmental, and societal contexts

5. ( Not Applicable ) An ability to function effectively on a team whose members together provide leadership, create a collaborative and inclusive environment, establish goals, plan tasks, and meet objectives

6. ( Not Applicable ) An ability to develop and conduct appropriate experimentation, analyze and interpret data, and use engineering judgment to draw conclusions

7. ( Not Applicable ) An ability to acquire and apply new knowledge as needed, using appropriate learning strategies.

Strategic Performance Indicators (SPIs)

Outcome 1 (Students will demonstrate expertise in a subfield of study chosen from the fields of electrical engineering or computer engineering):
1. Explain hardware modeling issues including representations, hardware languages and abstract hardware models such as dataflow and sequencing graphs.

Outcome 2 (Students will demonstrate the ability to identify and formulate advanced problems and apply knowledge of mathematics and science to solve those problems):
1. Analyze graph representations of logic networks and timing and apply logic minimization algorithms.

Outcome 3 (Students will demonstrate the ability to utilize current knowledge, technology, or techniques within their chosen subfield):
1. Design hardware at the architectural level using synthesis chip design tools.

Course Objectives

Topical Outline

1. Introduction to Logic Synthesis
2. Logic synthesis and two-level logic optimization
1. Quine-McClusky method for exact optimization, in psuedo-code.
3. Data structures for logic optimization, Heuristic two-level logic optimization
4. Binary Decision Diagrams
1. BDD theory. Logic operations on large input/output functions using BDDs.
5. Symbolic Minimization and Encoding Problems
1. State minimization and minimal state encoding using symbolic methods.
6. Multilevel Logic Synthesis
1. Representation and minimization of multiple-level logic networks.
7. Algebraic and Boolean Methods for multilevel logic network minimization
8. Timing Issues in Multi-Level Synthesis
1. Sensitizable paths, false paths and critical paths in logic networks.
9. FSM Optimization
1. Automated minimization of Finite State Machines.
10. Retiming
1. Moving of registers, repartitioning the logic network, to obtain a better solution.
11. Synchronous Logic Synthesis
1. Moving of registers to the periphery for logic minimization of larger logic block; synchronous don't cares.
12. Library Binding
1. Mapping a logic network to a particular standard cell library for a particular process
13. Introduction to High-level Synthesis
1. Describe enabling and strategic technology, application of VLSI circuit technology to the design and manufacture of computing, communication, and consumer products.
14. Modeling
1. Explain hardware modeling issues: representations, hardware languages, and abstract hardware models such as dataflow and sequencing graphs.
15. Verilog
16. FSM-based formalisms
1. Explain data-flow models and derivatives, focusing on computation.
17. Explain control-flow models, which are based on FSM models.
18. Esterel
1. Describe the Esterel language with its syntax and semantics.
19. Architectural synthesis
1. Compiling language models into abstract models, from which the architecture can be synthesized. Explain behavioral-level optimization and program-level transformations.
20. Scheduling
1. The scheduling problem, relative timing constraints, resource constraints, and heuristic methods to satisfy these constraints. PDF. Hu's algorithm, list scheduling, force-directed scheduling.
21. Resource sharing
1. Resource dominated circuits, flat and hierarchical graphs, functional and memory resources. Extensions to concurrent scheduling and binding.
22. Control synthesis
1. Synthesis of pipelined circuits, data-path synthesis, control-unit synthesis.
23. Dynamic Power management for circuits
1. Idleness and power management; clock gating, circuit partitioning, pre-computation, and data-path gating.
24. Dynamic Power management for systems
1. Frameworks such as ACPI and OnNow, power management policies.
25. Hardware/Software Co-Design
1. Components, technology, and design methodologies. Co-design of computers, embedded systems, reconfigurable systems. Computer-aided co-design: system modeling, validation and synthesis.