Design Synthesis of Application-Specific Signal Processors

This course is no longer offered

(2-0-0-3)

CMPE Degree: This course is Elective for the CMPE degree.

EE Degree: This course is Elective for the EE degree.

Lab Hours: 0 supervised lab hours and 0 unsupervised lab hours.

Technical Interest Group(s) / Course Type(s): Digital Signal Processing

Course Coordinator: Vijay K Madisetti

Prerequisites: ECE 4270

Catalog Description

Fundamentals of theory and practice of DSP chip design in VHDL. Exposure
to tools and environments for chip design, simulation, and verification.

Textbook(s)

Digital Signal Processing with Programmable Gate Arrays

Course Outcomes

Not Applicable

Strategic Performance Indicators (SPIs)

Not Applicable

Topical Outline

[6 hours] Introduction to DSP processors and ASICs
Transformational and Reactive Systems
Charactersitics of DSP applications
Characteristics of DSP architectures

[9 hours] DSP Datapath Design
Arithmetic Unit Design
Pipelining issues and control
Flow graph optimizations
Examples

[15 hours] VHDL Language Fundamentals
Language fundamentals
Simulation-based Design
Laboratory issues

[9 hrs] Register Transfer Level Chip Design
FSM models
Synthesis issues
Verification

[3 hrs] Filter and FFT chip designs

[3 hrs] Exams