The fellowship offers Ph.D. students Julian Arenas and Kevin Patiño-Sosa a valuable opportunity to collaborate with Apple engineers, receive academic support, and apply their research to real-world silicon challenges.
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Apple’s New Silicon Initiative (NSI) was launched to meet the growing demand for U.S.-based talent in integrated circuit (IC) design and computer architecture. Georgia Tech joined the program in 2024, adding to a select group of NSI universities, offering students unique opportunities to deepen their expertise in microelectronic circuits and hardware design.
A highlight of Georgia Tech’s first NSI year was the Ph.D. Fellowship in Integrated Circuits and Systems. Students Julian Arenas and Kevin D. Patiño-Sosa were selected as the Apple NSI Ph.D. Fellows, rising to the top of a highly competitive pool.
The fellowship provides a summer internship at Apple, full academic year funding, and direct mentorship from Apple engineers.
Both Apple NSI Ph.D. Fellows expressed enthusiasm about the opportunity and the impact it’s already having on their education and research:
“The NSI Fellowship means I can share my research with a wide spectrum of Apple engineers,” said Arenas. “From digital controllers to voltage regulation schemes, it’s incredible to get Apple’s perspective and align our work with real-world product design.”
“Being supported by Apple validates the relevance of my research and gives me access to a community of engineers pushing the limits of silicon innovation,” said Patiño-Sosa. “The feedback I’ve received has directly shaped my work on domain-specific processors. It’s a powerful reminder of how industry engagement can elevate academic impact.
Below, you can learn more about the Fellows and their research:
Julian Arenas, Fourth-year Ph.D. Student
Processing Systems Lab (PSyLab)
Advised by Visvesh Sathe
Julian Arenas is from Bucaramanga, Colombia, a small city on the east side of the country. He received his B.S. and M.S. from the University Industrial de Santander in 2018 and 2021, respectively. Arenas joined Associate Professor Visvesh Sathe’s Processing Systems Lab (PsyLab) in 2021. He has held internship positions at IMEC and NXP, working in high-speed circuits and DC/DC converters. He also worked on digital voltage regulation during the summer at Apple. Outside of his academic pursuits, Arenas enjoys playing chess, reading novels, and playing video games.
What are your research interests?
Clocking, voltage regulation, and the use of design and run-time computational techniques to enhance power management systems.
What led you to get involved with the Apple NSI program?
I have participated in the NSI kickoff meetings that Apple has held at Georgia Tech since 2023. It was an incredible opportunity to meet Fernando Mujica (Ph.D. ECE '99) and all the Georgia Tech alumni working at Apple.
What does this opportunity mean to you?
This is a big milestone for me. Being part of Apple’s New Silicon Initiative lets me connect my research with what’s happening in the industry. I’ve gotten feedback straight from top engineers, especially in areas like voltage regulation and predictive designs—and that’s made my Ph.D. work way stronger. It’s not just an honor; it is the chance of making my research part of a real product.
What are your professional goals or plans?
I want to be part of industry in the short term and absorb as much knowledge as possible. My long-term goal is to go back to academia and motivate the next engineers by being a professor myself.
How will this fellowship help you reach those goals?
I have had the chance to meet and connect with Apple engineers, former NSI fellows, other professors, students, etc. There is unexpected brainstorming, and ideas are coming from the least expected place. Maybe it is too soon to tell, but I am pretty sure the people I met through this fellowship will still be part of my short- and long-term network and, therefore, will help in my future goal of staying in academia.
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Kevin D. Patiño-Sosa, Sixth-year Ph.D. Student
Processing Systems Lab (PSyLab)
Advised by Visvesh Sathe
Kevin D. Patiño-Sosa is also a Ph.D. student in Sathe’s PsyLab. Originally from Bogotá, Colombia, he began his doctoral studies in 2020 at the University of Washington and transferred to Georgia Tech in 2022. He holds M.Sc. and B.Sc. degrees in electronic engineering from Universidad Nacional de Colombia, as well as an M.Sc. in electrical engineering from the University of Washington.
From 2018 to 2020, Patiño-Sosa was a visiting research scholar at the Neuromodulation Research Center at the University of Minnesota, where he developed a brain-computer interface capable of executing real-time closed-loop stimulation algorithms in both in-vitro and in-vivo models. Prior to that, he worked as a hardware engineer lead at MATRIX Labs, a Miami-based startup, contributing to the design and commercialization of the MATRIX Creator and MATRIX Voice platforms.
In 2024, he joined Intel Corporation as a research engineer intern, focusing on on-chip logic techniques to improve SoC resilience and reliability under process, voltage, and temperature variations.
What are your research interests?
I'm passionate about signal processing and computer architecture, particularly in the context of neuro-engineering and speech recognition systems. My current research at PSyLab focuses on designing domain-specific processors and hardware architectures for neural engineering applications. This includes low-power neural signal processing units, hardware accelerators for filtering and feature extraction, and integrated systems for closed-loop neuromodulation. I'm especially interested in applying Digital VLSI design techniques to build efficient, scalable systems that enable real-time performance and bridge the gap between algorithm development and hardware implementation.
What led you to get involved with any of the Apple NSI program?
I participated in the inaugural 65nm SoC tapeout class at Georgia Tech, which is now part of Apple’s New Silicon Initiative. I led the top-level integration of the system-on-chip, which included a RISC-V core and six student project tiles. My work involved implementing a DLL for clock skew mitigation and enabling voltage scaling across tiles. In addition to the design phase, I also supported post-silicon validation by guiding students through the chip testing process—sharing lab time, offering technical advice, and helping debug hardware issues during bring-up.
What does this opportunity mean to you?
This opportunity represents a pivotal moment in my academic and professional journey. Being part of the Apple New Silicon Initiative connects my research with industry-leading perspectives and provides direct access to feedback from world-class engineers. Their guidance—especially in areas like power architecture, DVFS, and multi-domain design—has helped me sharpen the technical foundation of my Ph.D. work. It’s both an honor and a unique chance to align my research with the real-world challenges faced in advanced silicon design. This experience reinforces my commitment to building impactful, energy-efficient digital systems.
What are your professional goals or plans?
My current professional goal is to complete my Ph.D. in ECE, with a strong focus on digital design, signal processing, and system-level hardware architecture. After graduation, I intend to pursue a career in the semiconductor industry, where I can contribute to the development of innovative, high-performance digital systems and continue advancing my expertise in VLSI and ASIC design.
How will this fellowship help you reach those goals?
Academically, this fellowship is helping me enhance the technical rigor of my dissertation by integrating industry-driven insights into power-aware system design. It’s pushed me to think more critically about real-world constraints and design scalability. Professionally, it’s an invaluable steppingstone toward a career in the semiconductor industry. Engaging with Apple’s engineering teams—both through the fellowship and my upcoming internship with the CPU implementation team—gives me direct experience with industry-standard design methodologies and strengthens my readiness to contribute to advanced digital hardware development.
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