The Center for the Co-Design of Cognitive Systems (CoCoSys) held its second annual review at Georgia Tech earlier this month, highlighting research projects conducted through the Center over the past year.
CoCoSys is one of seven Joint University Microelectronics Program (JUMP) 2.0 academic research centers co-sponsored by the Semiconductor Research Corporation and Defense Advanced Research Projects Agency (DARPA).
The Center aims to enable the next generation of collaborative human-AI systems through synergistic advances in algorithms, hardware motifs, algorithm-hardware co-design, and collective and collaborative intelligence.
The event brought together leading experts from the 10 CoCoSys partner universities from across the country working on AI technology — from algorithms and software to new hardware substrates — to share accomplishments, insights, and collaborations with industry and government sponsors, including those from IBM, Samsung, and Intel.
"Gathering CoCoSys researchers, students, and partners in person at the annual review is an important part of the collective progress in advancing the Center’s mission,” said Professor Arijit Raychowdhury, who co-directs the Center. “Being together in person facilitates invaluable opportunities for learning and meaningful connections. Thanks to everyone for their hard work and dedication, and special appreciation to the organizers for successfully planning and hosting such an important meeting."
Research being presented at the Second Annual CoCoSys Review. Viewers got a look at the Center's research and a preview of it's future goals over the course of the two-day event.
Raychowdhury, the Steve W. Chaddick School Chair in the School of Electrical and Computer Engineering (ECE), co-leads the Center along with Anand Raghunathan of Purdue University.
CoCoSys co-director and Steve W. Chaddick School Chair in the School of Electrical and Computer Engineering Arijit Raychowdhury giving remarks at the Center's annual review.
Overall, there were 140 attendees, including:
- 75 student presenters, which includes students and post-docs, presenting posters and demonstrations
- 21 principal investigators from 10 universities: UC San Diego, UC Berkeley, Stanford, Purdue, University of Minnesota, Cornell Tech, University of Illinois Urbana-Champaign, MIT, Yale, and, of course, Georgia Institute of Technology
- 25 industry and government representatives from SRC, DARPA, Analog, Boeing, EMD Group, GlobalFoundries, IBM, Intel, MediaTek, Micron, Raytheon, Samsung, SK hynix, and TSMC.
JUMP 2.0 representatives, including director Roman Caudillo and program manager for innovative research Adam Knapp, along with Dev Palmer, the managing director next-generation microelectronics manufacturing at DARPA, gave presentations regarding the state of JUMP.
“I am so excited to see the full blossoming of JUMP 2.0’s research in its second year of operation," Knapp said. "While our program spans the full stack of semiconductors and their use cases, CoCoSys’s research lives within AI and cognitive computing at the top of the stack and has the potential to leverage much of the work done in other centers. This year we saw amazing new results in areas as diverse as neuro-symbolic computing, hyper dimensional in-memory compute and AI chiplets and we look forward to what future years will bring.”
Awards were also given for outstanding research done through the Center.
ECE Ph.D. candidates Zishen Wan, Ritik Raj, and Hanchen Yang were honored with the Best Collaborative Poster Award for their work “CogSys: Efficient and Scalable Neuro-Vector-Symbolic Cognition System via Algorithm-Hardware Co-Design.”
Xiaofan Yu from the University of California San Diego, Soonha Hwang from the University of Illinois Urbana-Champaign, Hyung Joon Byun from Cornell Tech, and Edward Sadler from Kennesaw State University also received awards.
At the conferences researchers identified goals they want to achieve in their four main areas of research in the coming year:
- Theme I: Neural, Symbolic, and Probabilistic Algorithms
- Develop methods for ambiguous object recognition under occlusion
- Develop probabilistic programs to perform optimal & approximate inference
- Test and debug the alpha version of Brain-Score
- Develop methods to learn shapes and transformations from images in an unsupervised manner and explore new encoding methods for HDC;
- Verify the capabilities of the proposed image grammar framework in detecting patch corruptions validate “image grammar”
- Incorporating Lagrange multipliers into coupled- oscillator models for optimization
- Explore methods to improve the robustness to common corruptions.
- Theme II: Hardware Algorithm Co-Design
- Define compelling theme-wide benchmarks and prototypes
- Make results widely available over the center and beyond
- Theme III: Hardware Algorithm Motifs
- Further development of vertical end-to-end technology evaluation.
- Efficient HW implementation/prototyping of algorithms
- Theme IV: Collaborative Intelligence.
- Further development of multi-agent cross-collaboration across multiple modalities
- Efficient Integration of Theme I algorithms (HD Computing and Fully Homomorphic Encryption) in Federated Setups for Privacy and Efficiency
- Integrating Large Language Models in the Distributed Learning Pipeline
ECE Ph.D. candidates Zishen Wan, Ritik Raj, and Hanchen Yang alongside CoCoSys and JUMP 2.0 leadership with their Best Collaborative Poster Award.
One of the many research projects displayed at the CoCoSys second annual review.
A presentation from the CoCoSys annual review. Along with presentations, there were posters set up to show all the Center's research from the past year.
“There is so much excitement today from the rapid advances and new applications stemming from generative AI, large language models, transformers, and deep learning models," Caudillo said. "At the recent CoCoSys Year 2 Annual Review, we learned how CoCoSys researchers are inventing the future by combining neural, symbolic, and probabilistic algorithms in novel synergistic ways and pairing those new algorithms with the optimal hardware for the task at hand through co-design principles. In so doing, they are paving the way for the cognitive computing paradigms of tomorrow that will continue to build on the headline-catching performance of the AI of today but with improved energy efficiency, explainability, and robustness."
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