RISC Architectures

(3-0-0-3)

CMPE Degree: This course is Not Applicable for the CMPE degree.

EE Degree: This course is Not Applicable for the EE degree.

Lab Hours: 0 supervised lab hours and 0 unsupervised lab hours.

Technical Interest Group(s) / Course Type(s): Computer Systems and Software

Course Coordinator:

Prerequisites: ECE 6100

Catalog Description

An advanced design oriented class studying the design techniques and
operational principles of modern Superscalar RISC datapaths.

Course Outcomes

Not Applicable

Strategic Performance Indicators (SPIs)

Not Applicable

Topical Outline

A Brief History of Computer Architecture
- Technology and Architecture
- RISC Design Philosophy
- Case Study: IBM 801, RISC 2, and MIPS-X

Exploiting Instruction-Level Parallelism
- Hazards and Instruction Scheduling
- Instruction Dispatch, Issue, and Retirement
- Reorder & Renaming Buffers
- Dynamic Scheduling and Speculative Execution
- Superscalar versus Superpipelining
- Case Study: Motorola PowerPC 620 and DEC Alpha 21164

Intel 80x86 Instruction Set: A RISC in CISC Clothing
- ISA Limits
- Runtime ISA Translation
- Case Study: AMD T5 and Intel P6

Compilation Issues
- Instruction Set Architecture
- Dependency Graphs and Register Allocation
- Static Instruction Reordering
- Branch Scheduling

Very Long Instruction Word Architectures
- Trace Scheduling
- Case Study: Multiflow Trace

Tomorrow's Microprocessors
- Multithreading
- Multiprocessor PCs
- Case Study: SUN UltraSPARC, HP VLIW