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Sarkar Awarded Qualcomm Innovation Fellowship

Atlanta, GA
Rishov Sarkar, a second-year Ph.D. candidate in the Georgia Tech School of Electrical and Computer Engineering (ECE)

Rishov Sarkar, a second-year ECE Ph.D. candidate, presenting the Vision Transformer FPGA demo at the University Demonstration at DAC, which represents a portion of the work proposed for the Qualcomm Innovation Fellowship.

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Rishov Sarkar, a second-year Ph.D. candidate in the Georgia Tech School of Electrical and Computer Engineering (ECE), has been awarded a Qualcomm Innovation Fellowship.

The Qualcomm Innovation Fellowship (QIF) program invests in Ph.D. students across a broad range of technical research areas. Award winners earn a one-year fellowship and are mentored by Qualcomm engineers to facilitate the success of the proposed research.

Sarkar is a member of ECE’s Software/Hardware Co-Design for Intelligence and Efficiency (SHARC) Lab direct by assistant professor Cong (Callie) Hao. He received his B.S. degree in 2020 in computer engineering with a minor in robotics and his M.S. degree in 2021 in electrical and computer engineering, both from Georgia Tech. His research lies primarily in developing FPGA (field programmable gate array) accelerators for Graph Neural Networks using High-Level Synthesis.

The Qualcomm Innovation Fellowship was awarded to Sarkar along with Zhiwen Fan from the University of Texas-Austin for their joint proposal, “Real-time Visual Processing for Autonomous Driving via Video Transformer with Data-Model-Accelerator Tri-Design.”

Qualcomm Research’s top engineers carefully review submitted proposals and select the QIF finalists, who are then invited to present their proposals to a panel of executive judges. The QIF program has experienced continued growth with over 100 proposals submitted each year in the U.S. and internationally, and has awarded over $15 million since it started in 2009 at Qualcomm’s Research Center in Silicon Valley, Cali.

In addition to the Qualcomm Innovation Fellowship, Rishov was recently awarded third place in University Demo Best Demonstration at the 59th Design Automation Conference for his work on a Memory-Efficient FPGA Architecture for Multi-Task Vision Transformer using Mixture-of-Experts. He is also a recipient of the 2022 CRNCH Ph.D. Fellowship for his proposal, “Hyperscale Distributed GNN Training with Tri-Design: Near-Storage, Device, and System.”

 

Last revised September 12, 2022