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Center for Advanced Electronics through Machine Learning Receives Phase II Funding from The National Science Foundation

As the global demand for microelectronics continues to surge, CAEML's mission to apply machine learning to the design of optimized microelectronic circuits and systems has become even more crucial.

Atlanta, GA
Madhavan Swaminathan

Madhavan Swaminathan

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As the global demand for microelectronics continues to surge, the mission of the Center for Advanced Electronics through Machine Learning (CAEML) to “apply machine learning to the design of optimized microelectronic circuits and systems” has become even more crucial. As part of Phase I funding from the National Science Foundation (NSF), CAEML researchers and students worked closely with industry partners to develop models and design tools to enable efficient and reliable fabrication of microelectronic systems while protecting intellectual property. With the new Phase II funding, this effort is expected to grow significantly through increased interest and partnership from the semiconductor industry.

“Design space exploration and optimization have had limited success in the past due to slow simulators,” said Madhavan Swaminathan, CAEML site director at Georgia Tech. “In Phase I we have repeatedly shown that machine learning based methods can significantly improve computational time and enhance productivity. These advantages have been quantified by several CAEML industry partners through deployment of these techniques into their workflow.”

During phase I, the team published more than 70 papers, delivered 20 webinars, and received 11 awards or award nominations for their work with the Center. In addition, 12 students who participated in CAEML’s Phase I research have been hired by industry partners.

CAEML is part of the NSF’s Industry-University Cooperative Research Center (IUCRC) program and includes faculty from Georgia Tech, the University of Illinois Urbana-Champaign (UIUC), and North Carolina State University (NCSU). Phase II is a five-year award and begins August 1, 2022.

“In Phase II we plan to address the end-to-end system design challenges by developing solutions to five technical challenges posed by industry using machine learning in the areas of analog circuit design, signal integrity, hardware security, reliability, and data access,” said Swaminathan, who also serves as the John Pippin Chair in Microsystems Packaging and Electromagnetics and Director of the Packaging Research Center at Georgia Tech.

In addition to Swaminathan, the leadership team for CAEML consists of Elyse Rosenbaum, Melvin and Anne Louise Hassebrock Professor in Electrical and Computer Engineering, UIUC and Paul Franzon, Cirrus Logic Distinguished Professor of Electrical and Computer Engineering and Director of Graduate Programs in Electrical and Computer Engineering at NCSU.

Read the full press release.

Last revised May 20, 2022