Five Ph.D. students from the Georgia Tech School of Electrical and Computer Engineering (ECE) won Best Paper in Session Awards at SRC TECHCON 2014, the most of any university attending the conference. TECHCON was held September 7-9 in Austin, Texas and is organized annually by Semiconductor Research Corporation to showcase a selected set of SRC-sponsored research.

The award-winning ECE students include William Song, William Wahby, Yarui Peng, Monodeep Kar, and Khondker (Zakir) Ahmed. Descriptions of their papers and their work follow.

William Song took top honors in the System Design: Architectures and Thermal/Reliability Management Session. His paper, entitled "Lifetime Reliability Characterization and Management of Many-Core Processors," represented the work of the Computer Architecture and Systems Laboratory, led by his Ph.D. advisor and ECE Professor Sudhakar Yalamanchili. Yalamanchili and ECE Associate Professor Saibal Mukhopadhyay were Song’s coauthors on the paper.

Song’s paper presents a characterization method for understanding how parallel applications create reliability variation in a multicore processor and how such variability is projected onto processor-level lifetime reliability. The key observation in Song’s paper leads to proposals for dynamic reliability management techniques that minimize the variance of reliability distribution on a multicore die and balance long term reliability-performance tradeoffs.

William Wahby won the award in the 3D Session. His paper was entitled “A Virtual Integration Platform for 3DIC Design Space Exploration” and was co-authored by his colleagues in the Integrated 3D Systems (I3DS) Research Group, Li Zheng and Yang Zhang, and his Ph.D. research advisor and ECE Associate Professor Muhannad Bakir.

Wahby’s paper described the development of a pathfinding tool to aid in the development of next generation 3D integrated circuits. To create the tool, he combined novel models developed by the I3DS Lab to account for wire length, power consumption, power delivery, and heat transfer in 3DICs.

To demonstrate its capabilities, the simulation tool was used to investigate the performance and power implications of transforming a conventional 32nm CPU core into a monolithic 3D design. The pathfinding tool allows researchers and engineers to rapidly compare the impacts of new technologies on future designs and to better understand the true costs and benefits of different design methodologies.

Yarui Peng received the top prize in the Circuit Design Tools Session. His paper was entitled “Fast and Accurate Full-Chip Extraction and Optimization of TSV-to-Wire Coupling” and was co-authored by Dusan Petranovic, a researcher at Mentor Graphics, and Peng’s Ph.D. advisor and ECE Professor Sung Kyu Lim. The paper presented research performed in the Georgia Tech Computer-Aided Design (GTCAD) Lab, led by Lim, in the area of parasitic extraction for 3DICs.

This paper shows the first demonstration of modeling and extraction of parasitic capacitance between Through-Silicon Vias (TSVs) and their surrounding wires in a 3D integrated circuit. For a fast and accurate full-chip extraction, the authors proposed a pattern-matching-based algorithm that considers the physical dimensions of TSVs and neighboring wires and captures their field interactions.

The team’s extraction method is accurate within 1.9 percent average error for a full-chip-level design while requiring negligible runtime and memory compared with a field solver. To reduce TSV-to-wire coupling, the authors presented two full-chip optimization methods that increase keep-out-zone and guard ring protection that are shown to be highly effective in noise reduction with minimal overhead.

Monodeep Kar took top honors in the Analog Design Tools Session for his paper entitled "Impact of the Process Variation in Inductive Integrated Voltage Regulators.” His co-authors were Sergio Carlo, a fellow Ph.D. researcher; Harish Krishnamurthy, a researcher at Intel Labs; and Kar’s and Carlo’s Ph.D. advisor and ECE Associate Professor Saibal Mukhopadhyay.

The paper studied a critical challenge – the variation in process parameters – in the deployment of an Integrated Voltage Regulator (IVR) for high-performance microprocessors. The paper studied the effects of variations in integrated passives, power train FETs, and controller transistors. Compared to an off-chip VR, Kar and his team’s findings showed that variations in IVR induce much larger shifts in the transient response of the IVR and power loss. The study also provides critical insight on how to design robust IVRs.

Khondker (Zakir) Ahmed won the award in the System Design with Sensors Session. His paper was entitled "Multi-Domain Power Delivery System for Microwatt Wireless Sensor Networks” and was co-authored by his Ph.D. advisor and ECE Associate Professor Saibal Mukhopadhyay.

Harvesting energy from the environment is an attractive approach for powering ultra-low-power wireless sensor nodes. Ahmed's paper presented a power delivery system for wireless sensor network electronics that are capable of harvesting from 10mV input and generates two domains by cascaded boost (up to 3V) and cascaded buck-boost (0.5V-1.2V) for RF supply and digital load supply, respectively. The system delivers RF and digital loads with a combined efficiency of 72 percent at 33mW and 10mW respectively, and consumes 280nA bias current. The design provides an interesting approach to address the critical power delivery and management challenges for ultra-low-power devices. 

Both Kar’s and Ahmed’s papers presented research performed in the Gigascale Reliable Energy Efficient Nanosystem (GREEN) Lab, led by Mukhopadhyay, in the area of integrated voltage converters and regulators for powering integrated circuits. These awards are recognitions of innovative, practical, and high-impact research being performed in ECE in the critical area of power delivery of electronic systems.