Updates on the campus response to coronavirus (COVID-19)

Ph.D. Proposal Oral Exam - Nael Mizanur Rahman

Event Details

Friday, August 19, 2022

3:00pm - 5:00pm


For More Information


Event Details

Title:  On-chip Power Supply Noise Sensing and Regulation for Secure and High Performance Compute Accelerators


Dr. Mukhopadhyay, Advisor   

Dr. Swaminathan, Chair

Dr. Krishna

Abstract: The objective of the proposed research is to demonstrate a lightweight Power Supply Noise (PSN) sensing and regulation scheme for active voltage regulation as well as Power Side Channel Attack (PSCA) detection, in high performance compute engines. Pipeline registers, implemented to increase max frequency and throughput in hardware, are prone to PSCA as their synchronous logging of data can be easily isolated from measurements of dynamic power variations. These measurements can then be used in statistical analysis to extract secret information from the system under attack. We first demonstrate a key-diffusion aware pipelining methodology on a PRINCE encryption algorithm in a 65nm CMOS test-chip. We show that by leveraging the key-dependancy of the plaintext in the encryption datapath, a pipeline register can be placed in such as way so as to maximise the complexity of the power model in a Correlation Power Attack (CPA), thereby making it less effective. However, PSCA is not fully eliminated as the combinational logic of the encryption engine is still prone to PSCA given sufficient measurements. We then present a PSCA detection scheme to completely thwart PSCA, using an on-chip lightweight PSN sensor implemented in 65nm CMOS test-chip. In order to perform a PSCA, a resistor (usually 1Ω) is placed on the power supply node under attack. Our on-chip sensor, placed on the target supply node, detects the presence of an attack resistor by passive monitoring of input voltage variations. Once detected, this shuts down the encryption engine, preventing an attacker from carrying out a PSCA. In the next step, we propose an on-chip integrated system of lightweight PSN sensor and digitally synthesizable voltage regulator (IVR,DLDO) implemented on a high throughput digital accelerator. We leverage the sensitivity of the proposed detector to voltage variations to provide closed loop on-chip supply monitoring and regulation in the presence of PSN while also enabling PSCA detection.

Last revised August 8, 2022